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[VHDL-FPGA-Verilog] FPGA_SPI.ZIP

Description: 实现了FPGA以SPI协议传送和接受16位数据。传送过程无需Nios核干预-SPI protocol to achieve the FPGA to send and receive a 16-bit data. Nios nuclear transfer process without intervention
Platform: | Size: 1024 | Author: shoucql | Hits:

[VHDL-FPGA-Verilog] VHD_Veri_spi

Description: 一个强大的符合SPI规范的VHDL/Verilog源码文件，传输模式和时钟相位均可以指定，采用同步时钟设计，可以工作在很高的频率下。支持主机及从机模式，强烈推荐使用！-A strong line with SPI standard VHDL/Verilog source files, transfer mode, and clock phase are to specify, using synchronous clock design can work in very high frequency. Support the host and slave mode, strongly recommended!
Platform: | Size: 13312 | Author: 中国 | Hits:

[VHDL-FPGA-Verilog] AD9512_VHDL

Description: FPGA通过SPI总线控制Analog公司的射频时钟分配芯片的程序，在需要用到高速时钟（GHz）的电路中经常采用，比如数据采集卡及信号回放卡中会经常用到该功能，已经在产品中得到验证，工作稳定。-The VHDL code of controlling AD9512 of Analog Device
Platform: | Size: 3072 | Author: 傅其祥 | Hits:

[VHDL-FPGA-Verilog] spi_write

Description: 对spi接口的flash操作，用VHDL语言实现，read，write，擦除的接口电路控制-Spi interface on the flash operation, with the VHDL language, read, write, erase controls the interface circuit
Platform: | Size: 1024 | Author: 王伯祥 | Hits:

[VHDL-FPGA-Verilog] SpiMaster

Description: This a verilog code for SPI Master testbench is also provided spi_top.v Xilinx ISE or Icarus verilog to compile and simulate-This is a verilog code for SPI Master testbench is also provided spi_top.v Xilinx ISE or Icarus verilog to compile and simulate
Platform: | Size: 9216 | Author: RutaliMulye | Hits:

[VHDL-FPGA-Verilog] SD_SPI

Description: sd卡spi接口的verilog程序，quartus2,全部调好能已经应用于SD卡模块。-sd card spi interface verilog program, quartus2, all tuned to have been used in SD card module.
Platform: | Size: 2700288 | Author: 洪传荣 | Hits:

[VHDL-FPGA-Verilog] VHDL-based-design-of-SPI

Description: 基于VHDL的串行同步通信SPI设计 本设计是用Quartus作为开发环境，以DE2板为硬件平台实现的SPI同步串行通讯。设计过程方便。根据接收和发送两个主要部分实现了SPI的基本功能。此外，该设计还实现了波特率发生器，数码管显示的功能。用DE2板实现具有电路简洁，开发周期短的优点。充分利用了EDA设计的优点。开发过程用了VHDL硬件描述语言进行描述，从底层设计，分模块进行，充分提高了设计者的数字逻辑设计的概念。-VHDL-based SPI serial synchronous communication design as the design is the use of Quartus development environment to DE2 board as the hardware platform of the SPI synchronous serial communication. Facilitate the design process. According to both send and receive SPI implements the main part of the basic functions. In addition, the design also implements the baud rate generator, digital display features. DE2 board to achieve a circuit with a simple, short development cycle advantages. Full use of the EDA design advantages. Development Process VHDL hardware description language used to describe the design from the ground, sub-module, to fully enhance the designer' s concept of digital logic design.
Platform: | Size: 51200 | Author: 陈添 | Hits:

[VHDL-FPGA-Verilog] SPI_interface(VHDL)

Description: SPI接口模块源代码（VHDL）语言，经过产品应用测试。-SPI interface module source code (VHDL language), after product application testing.
Platform: | Size: 1024 | Author: Field | Hits:

[VHDL-FPGA-Verilog] spiflash

Description: VHDL language to read and write of the SPI FLASH
Platform: | Size: 371712 | Author: myname | Hits:

[VHDL-FPGA-Verilog] CoreSPI_21_eval

Description: SPI IP核源码，包括Verilog和VHDL两种语言源码-SPI IP core source code, including the two languages ​ ​ Verilog and VHDL source code
Platform: | Size: 628736 | Author: 任林枫 | Hits:

[VHDL-FPGA-Verilog] spi_int

Description: realize spi interface vhdl code xilinx help ths help developers
Platform: | Size: 65536 | Author: Antoshka | Hits:

[VHDL-FPGA-Verilog] spi_dac

Description: driver for spi DAC in VHDL
Platform: | Size: 1024 | Author: Hung | Hits:

[VHDL-FPGA-Verilog] spi

Description: 描述了总线的vhdl程序，并且有测试语句的描写 仿真之后可以实现-Describes the bus vhdl program, and a test statement, after describing the simulation can be achieved
Platform: | Size: 1024 | Author: 王韩 | Hits:

[VHDL-FPGA-Verilog] Altera-memory

Description: 这个软件是altera 芯片对SPIflash的一个控制程序，里面读写测试已经通过。-spi flash code for VHDL
Platform: | Size: 125952 | Author: 周明 | Hits:

[VHDL-FPGA-Verilog] spi

Description: 一个vhdl开发的spi总线的控制程序，很有广泛性，可做参考-spi based on vhdl
Platform: | Size: 2048 | Author: coolxgz | Hits:

[VHDL-FPGA-Verilog] spi

Description: Altera Cyclone SPI-slave vhdl module
Platform: | Size: 491520 | Author: xornonop | Hits:

[VHDL-FPGA-Verilog] VHDL-SPI-Module

Description: This an small program which write in VHDL it is mainly used to read/write serial data by SPI model -This is an small program which write in VHDL it is mainly used to read/write serial data by SPI model
Platform: | Size: 51200 | Author: bob lee | Hits:

[assembly language] spi

Description: spi总线结构设计和实现用vhdl汇编语言编写的 -spi for verilog hardware description language
Platform: | Size: 5120 | Author: 张焕然 | Hits:

[VHDL-FPGA-Verilog] SPI-Master-Core-DAC-ADC-spartan

Description: SPI Master Core for spartan (ADC, DAC) vhdl code
Platform: | Size: 1961984 | Author: onur | Hits:

[assembly language] SPI-Core_nguyen

Description: SPI Master Core HDL: VHDL 93 Compatibility: all FPGAs, CPLDs parameterization: - variable data width - Phase/polarity configurable - selectable buffer depth - serial clock devision due to system clock package usage: IEEE.STD_LOGIC_1164 IEEE.NUMERIC_STD work.general_signal_processing_pkg (included) Testbench for simulation included. Core Tested on Lattice XP2 CPLD Brevia development kit and FPGAs Xilinx Spartan-3E and Altera Cyclone-4E (industrial application)
Platform: | Size: 17408 | Author: AgentNguyex | Hits:
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